D. Appendix: Supported Events on Linux Intel Pentium 4 Platforms

Table 22 and Table 23 show all events that are supported on Intel Pentium 4 platforms when using perfctr under Linux (kernel patch, library). More detailed information about the performance events can be found in the IA-32 Software Developer's Manual [Int01].

Table 22: Supported Performance Events for Intel Pentium 4.

Event	description	PCL
TOT_CYCLES	cycles	PCL_CYCLES
TOT_INS_C	instructions completed	PCL_INSTR
TOT_INS_I	instructions issued
UOPS_C	uops completed
UOPS_I	uops issued
BR_INS	branch instructions retired	PCL_JUMP
BR_INS_P	branch instructions predicted
BR_INS_M	branch instructions mispredicted
BR_INS_T	branch instructions taken
BR_INS_N	branch instructions not taken
BR_INS_NP	branch instructions not taken pred
BR_INS_TP	branch instructions taken predicted	PCL_JUMP_SUCCESS
BR_INS_NM	branch instructions not taken misp
BR_INS_TM	branch instructions taken mispredict
BR_MPD	mispredicted branch instructions	PCL_JUMP_UNSUCCESS
FP_INS_C	floating point instructions completed	PCL_FP_INS
FP_INS_I	floating point instructions issued
S_SP_INS_C	scalar single-precision uop completed
S_SP_INS_I	scalar single-precision uop issued
S_DP_INS_C	scalar double-precision uop completed
S_DP_INS_I	scalar double-precision uop issued
P_SP_INS_C	packed single-precision uop completed
P_SP_INS_I	packed single-precision uop issued
P_DP_INS_C	packed double-precision uop completed
P_DP_INS_I	packed double-precision uop issued
MMX_64_INS_C	64-bit MMX uops completed
MMX_64_INS_I	64-bit MMX uops issued
MMX_128_INS_C	128-bit integer SIMD instr completed
MMX_128_INS_I	128-bit integer SIMD instr issued
VEC_INS_C	vector instr (MMX/SSSE2) completed

Table 23: Supported Performance Events for Intel Pentium 4.

Event	description	PCL
LD_INS	load instruction completed	PCL_LOAD_INSTR
SR_INS	store instruction completed	PCL_STORE_INSTR
LD_SR_INS	load or store instruction completed	PCL_LOADSTORE_INSTR
L1_I_MISS	Level-1 Instruction/Trace Cache Miss	PCL_L1ICACHE_MISS
L1_MISS_R	Level-1 Cache miss (load replayed)	PCL_L1DCACHE_MISS
L2_READ	Level-2 Cache read	PCL_L2CACHE_READ
L2_HIT	Level-2 Cache hit	PCL_L2CACHE_HIT
L2_HIT_S	Level-2 Cache hit shared
L2_HIT_M	Level-2 Cache hit exclusive
L2_HIT_E	Level-2 Cache hit modified
L2_MISS	Level-2 Cache miss	PCL_L2CACHE_MISS
L2_MISS_R	Level-2 Cache miss (load replayed)
PW_ITLB	Page walk for ITLB miss
ITLB_READ	ITLB reference
ITLB_HIT	ITLB reference hit
ITLB_MISS	ITLB reference miss	PCL_ITLB_MISS
DTLB_MISS	DTLB miss (page walks)	PCL_DTLB_MISS
DTLB_MISS_R	DTLB miss (load/store replayed)
DTLB_LD_MISS_R	DTLB miss (load replayed)
DTLB_SR_MISS_R	DTLB miss (store replayed)
BUS	bus requests
BUS_NP	bus requests - no prefetch